CEU Camera Usage Instructions
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Introduction
This example demonstrates how to use the CEU (Camera Engine Unit) interface on the Titan Board to connect an OV5640 camera, and display the captured images on an RGB565 LCD screen via the RT-Thread LCD framework.
Key functionalities include:
Initialize the CEU camera interface to capture real-time video streams
Configure OV5640 camera parameters (resolution, frame rate, output format)
Display captured images using the RT-Thread LCD driver
Support image format conversion (YUV422 → RGB565)
RA8 Series CEU (Camera Engine Unit) Features
The RA8 series MCU integrates a CEU hardware module for efficient capture of camera image data, supporting multiple image formats and resolutions, and enabling direct transfer to memory or display interfaces.
1. CEU Hardware Interface Features
Interface Types
DVP (Digital Video Port) interface for connecting CMOS cameras
Supports 8/10/12-bit data bus
Synchronization signals:
PCLK: Pixel clock
HSYNC: Line synchronization
VSYNC: Frame synchronization
Input Resolution and Frame Rate
Supports VGA, QVGA, SXGA, UXGA, and other common resolutions
Frame rates from 1–60 fps, configurable for different applications
Camera Compatibility
Compatible with common CMOS cameras such as OV5640, OV7670
Supports auto-initialization and register configuration
2. Image Formats and Processing Capabilities
Supported Image Formats
YUV422 (commonly used for video transfer)
RGB565 (suitable for LCD display)
RAW10/RAW12 (for image processing and algorithm development)
Image Processing Features
Color space conversion: YUV ↔ RGB
Image cropping: capture only a specific ROI (Region of Interest)
Image scaling: support proportional scaling up or down
Mirror and flip: horizontal or vertical mirroring
Hardware Acceleration
CEU contains a hardware processing unit to reduce CPU load
Provides fast image format conversion and scaling
3. DMA Support and Buffer Mechanism
High-Speed DMA Transfer
Works with MCU DMAC for fast memory writes
Supports direct writing to frame buffer or LCD buffer
Multi-Buffer Mechanism
Supports double buffering or ring buffers for continuous video capture
Reduces frame loss and display latency
Flexible DMA Configuration
Configurable buffer start address and size
Supports interrupt triggering and callbacks
4. Interrupt Mechanism
Interrupt Types
Frame End Interrupt: triggered when each frame capture completes
Line End Interrupt (optional): triggered at the end of each line capture
Error Interrupt: including buffer overflow or sync signal anomalies
Interrupt Features
Supports RT-Thread ISR callback registration
Can work with DMA for real-time processing and display
5. Timing and Synchronization Features
Line/Frame Synchronization
HSYNC aligns each line of data
VSYNC aligns each frame
Pixel Clock
CEU supports external PCLK or internal clock division
Ensures synchronization with camera output to avoid sampling errors
Data Alignment
Supports byte or pixel alignment
Automatically adjusts according to image format
6. Performance and Optimization
High Throughput
DMA + double buffering enables continuous video capture
Low CPU usage suitable for real-time applications
Reliability
Sync signal anomalies trigger interrupts
Buffer overflow detection
Automatic recovery from frame loss
Flexibility
Supports multiple resolutions and format switching
Configurable cropping and scaling regions to improve display efficiency
7. Application Scenarios
Real-time video display on LCD
Video capture and image processing algorithm testing
Embedded vision applications, e.g., surveillance, gesture recognition, robotics vision
RA8 Series MCU GLCDC (Graphics LCD Controller) Features
The RA8 series MCU (e.g., RA8P1) integrates a GLCDC hardware module for driving TFT/LCD displays, enabling high-speed graphics rendering and video display, supporting multiple resolutions, color formats, and display modes.
1. Hardware Features
Resolution Support
Can drive common resolutions from QVGA (320×240) to WQVGA/XGA
Limited by on-chip RAM and display interface bandwidth
Color Support
Supports 1/4/8/16/24/32-bit color depth
Common formats: RGB565, RGB888
Supports palette mode (CLUT)
Hardware color conversion available
Interface Types
Parallel RGB (TFT LCD interface)
Supports 16/18/24-bit data bus
Direct connection to external LCD panels
Programmable timing: HSYNC, VSYNC, DE, PCLK, RGB output
2. Layers and Display Modes
Layer Support
Single-layer mode (single screen display)
Multi-layer mode (palette or hardware alpha blending)
Supports transparent/semi-transparent overlay
Display Modes
RGB mode (direct color output)
CLUT/Palette mode (indexed color via lookup table)
Configurable scan direction (horizontal/vertical)
3. DMA and Frame Buffer
Frame Buffer Access
GLCDC can directly access on-chip or external SRAM frame buffer
Supports single or double buffering
Supports ring buffer for continuous refresh
DMA Support
Works with MCU DMAC to reduce CPU usage
Can transfer images directly from memory to LCD
Supports line, block, or full-frame transfer
4. Hardware Graphics Functions
Window Cropping and Scaling
Can specify display window area
Supports simple horizontal/vertical scaling
Hardware Graphics Acceleration
Rectangle fill, color replacement
Image transparency processing
Can be combined with CEU or DMA for video display
Color Format Conversion
YCbCr → RGB
RGB888 → RGB565
Hardware accelerated to reduce CPU load
5. Interrupt Mechanism
Interrupt Types
Frame End
Line End (optional)
Access error/overflow
Interrupt Application
Integrates with RT-Thread ISR
Can trigger buffer update or double-buffer swap on frame completion
Enables smooth animations and video display
6. Performance Optimization
Double Buffer Mechanism
Reduces flicker
CPU can render next frame in background
GLCDC hardware automatically switches display buffer
Frame Rate Control
Programmable clock and line/frame synchronization
Supports common refresh rates (30fps, 60fps)
CPU Offload
Many graphics operations performed in hardware
DMA + GLCDC combination enables efficient image display
Hardware Description
The CEU camera interface and RGB LCD interface are shown in the following figure:

FSP Configuration
HyperRAM Configuration
Create a
r_ospi_bstack:

Configure the r_ospi_b stack:



HyperRAM pin configuration:

The drive capability of all pins related to HyperRAM should be configured as H, and OM_1_SIO0 to OM_1_SIO7 need to be configured as Input pull-up.

CEU Configuration
Create a
r_ceustack:

Configure CEU:

Configure CEU pins:

CEU Clock Configuration
Create a
r_gptstack:

Configure the camera clock PWM output:

D/AVE 2D Configuration
Create a
r_drwstack:

RGB LCD Configuration
Create a
r_glcdcstack:

Configure interrupt callback and graph layer 1:

Configure the output parameters, CLUT, TCON, and Dithering:

Configure GLCDC pins:


LCD Backlight Configuration
Create a
r_gptstack:

Configure back light PWM output:

RT-Thread Settings Configuration
Enable CUE camera, using i2c1 and ov5640 camera. Enable RGB565 LCD, using pwm7 output backlight.

Compilation & Download
RT-Thread Studio: In RT-Thread Studio’s package manager, download the Titan Board resource package, create a new project, and compile it.
After compilation, connect the development board’s USB-DBG interface to the PC and download the firmware to the development board.
Run Effect
After resetting the Titan Board, the terminal will output the following message:

Here is the image displayed on the LCD screen:
